View LPC3130_6998340.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra 1. general description the nxp LPC3130/3131 combine an 180 mhz arm926ej-s cpu core, high-speed usb 2.0 on-the-go (otg), up to 192 kb sram, nand flash controller, flexible external bus interface, four channel 10-bit adc, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industri al, medical, and communication markets. to optimize system power consumption, the LPC3130/3131 have multiple power domains and a very flexible clock generation unit (c gu) that provides dynamic clock gating and scaling. 2. features 2.1 key features ? cpu platform ? 1 80 mhz, 32-bit arm926ej-s ? 16 kb d-cache and 16 kb i-cache ? me mory management unit (mmu) ? internal memory ? 96 kb (LPC3130) or 192 kb (lpc3131) embedded sram ? ext ernal memory interface ? nand flash co ntroller with 8-bit ecc ? 8/16-bit multi-port memory co ntroller (mpmc): sdram and sram ? comm unication and connectivity ? hig h-speed usb 2.0 (otg, host, device) with on-chip phy ? tw o i 2 s-bus interfaces ? in tegrated master/slave spi ? t wo master/slave i 2 c-bus interfaces ? fa st uart ? memory card interface (mci): mmc/sd/sdio/ce-ata ? fo ur-channel 10-bit adc ? integ rated 4/8/16-bit 6800/8080 compatible lcd interface ? sys tem functions ? dynam ic clock gating and scaling ? multiple pow er domains ? se lectable boot-up: spi flash, nand fl ash, sd/mmc cards, uart, or usb ? dma c ontroller ? fo ur 32-bit timers LPC3130/3131 low-cost, low-power arm926ej-s mcus with high-speed usb 2.0 otg, sd/mmc, and nand flash controller rev. 1 .01 ? 21 may 2009 preliminary data sheet
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 2 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? watchdog timer ? pwm mod ule ? ra ndom number generator (rng) ? g eneral purpose i/o (gpio) pins ? fle xible and versatile interrupt structure ? jt ag interface with boundary scan and arm debug access ? oper ating voltage and temperature ? cor e voltage: 1.2 v ? i/o vo ltage: 1.8 v, 2.8 v, 3.3 v ? t emperature: ? 40 c to +85 c ? tf bga180 package: 12 12 mm 2 , 0.8 mm pitch 3. ordering information table 1. ordering information type number package name description version LPC3130fet180 tfbga180 plastic thin fine pitch ball grid array package, 180 balls, body 12 12 0.8 mm sot570-3 lpc3131fet180 tfbga180 plastic thin fine pitch ball grid array package, 180 balls, body 12 12 0.8 mm sot570-3 table 2. ordering options for LPC3130/3131 type number core/bus frequency total sram high-speed usb 10-bit adc channels i 2 s-bus/ i 2 c-bus mci sdhc/ sdio/ ce-ata temperature range LPC3130fet180 180 mhz/ 90 mhz 96 kb device/ host/otg 4 2 each yes ? 40 c to + 85 c lpc3131fet180 180 mhz/ 90 mhz 192 kb device/ host/otg 4 2 each yes ? 40 c to + 85 c
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 3 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 4. block diagram fig 1. LPC3130/3131 block diagram 96 kb isram0 arm926ej-s test/debug interface dma controller mci sd/sdio usb 2.0 high-speed otg ahb to apb bridge 0 async ahb to apb bridge 1 async jtag interface i2s0/1 i2c1 uart lcd spi system control pwm cgu i2c0 timer 0/1/2/3 wdt ioconfig 10-bit adc event router random number generator apb slave group 3 nand registers dma registers apb slave group 4 apb slave group 2 apb slave group 1 apb slave group 0 LPC3130/3131 master master master master slave 002aae124 slave slave slave ahb to apb bridge 2 async slave ahb to apb bridge 3 async slave ahb to apb bridge 4 sync slave slave 96 kb isram1 (1) slave rom interrupt controlller slave slave slave slave slave data cache 16 kb instruction cache 16 kb pcm mpmc nand controller buffer (1) lpc3131 only multilayer ahb matrix
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 4 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 5. pinning information 5.1 pinning fig 2. LPC3130/3131 pinning tfbga180 package 002aae130 LPC3130/3131 2 4 6 8 10 12 13 14 1357911 ball a1 index area p n m l k j g e h f d c b a transparent top view table 3. pin allocation table pin symbol pin symbol pin symbol pin symbol row a 1 ebi_d_10 2 ebi_a_1_cle 3 ebi_d_9 4 mgpio10 5 mgpio7 6 mgpio6 7 spi_cs_out0 8 spi_sck 9 vddi 10 ffast_in 11 vssi 12 adc10b_gnda 13 adc10b_vdda33 14 adc10b_gpa1 - - - - row b 1 ebi_d_8 2 vdde_ioa 3 ebi_a_0_ale 4 mnand_rybn2 5 mgpio8 6 mgpio5 7 spi_mosi 8 spi_cs_in 9 pwm_data 10 ffast_out 11 gpio3 12 vsse_ioc 13 adc10b_gpa2 14 adc10b_gpa0 - - - - row c 1 ebi_d_7 2 ebi_d_11 3 vsse_ioa 4 vsse_ioa 5 mgpio9 6 vddi 7 vssi 8 spi_miso 9 vddi 10 i2c_sda0 11 gpio4 12 vddi 13 vdde_ioc 14 adc10b_gpa3 - - - - row d 1 ebi_d_5 2 ebi_d_6 3 ebi_d_13 4 mnand_rybn3 5 vdde_ioc 6 vsse_ioc 7 vdde_ioc 8 vsse_ioc 9 vsse_ioc 10 i2c_scl0 11 vdda12 12 vssi 13 buf_tck 14 buf_tms - - - -
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 5 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers row e 1 ebi_d_3 2 ebi_d_4 3 ebi_d_14 4 vsse_ioa 5 vdde_ioa 6 mnand_rybn0 7 mnand_rybn1 8 vdde_ioc 9 vssa12 10 vdda12 11 arm_tdo 12 i2c_sda1 13 i2c_scl1 14 i2stx_bck1 - - - - row f 1 ebi_d_2 2 ebi_d_1 3 ebi_d_15 4 vsse_ioa 5 vdde_ioa 10 scan_tdo 11 buf_trst_n 12 i2stx_data1 13 i2srx_ws1 14 i2srx_bck1 - - - - row g 1 ebi_ncas_blout_0 2 ebi_d_0 3 ebi_d_12 4 vssi 5 vdde_ioa 10 i2stx_ws1 11 vsse_ioc 12 vdde_ioc 13 sysclk_o 14 i2srx_data1 - - - - row h 1 ebi_dqm_0_noe 2 ebi_nras_blout_1 3 vddi 4 vsse_ioa 5 vdde_ioa 10 gpio12 11 gpio19 12 clk_256fs_o 13 gpio11 14 rstin_n - - - - row j 1 nand_ncs_0 2 ebi_nwe 3 nand_ncs_1 4 clock_out 5 usb_rref 10 gpio1 11 gpio16 12 gpio13 13 gpio15 14 gpio14 - - - - row k 1 nand_ncs_2 2 nand_ncs_3 3 vsse_ioa 4 usb_vssa_ref 5 mlcd_db_12 6 mlcd_db_6 7 mlcd_db_10 8 mlcd_csb 9 tdi 10 gpio0 11 vdde_ioc 12 gpio17 13 gpio20 14 gpio18 - - - - row l 1 usb_vdda12_pll 2 usb_vbus 3 usb_vssa_term 4 vdde_iob 5 mlcd_db_9 6 vssi 7 vddi 8 mlcd_e_rd 9 vsse_ioc 10 vdde_ioc 11 vssi 12 vddi 13 vsse_ioc 14 gpio2 - - - - row m 1 usb_id 2 usb_vdda33_drv 3 vsse_iob 4 vsse_iob 5 vdde_iob 6 vsse_iob 7 vdde_iob 8 vsse_iob 9 vdde_iob 10 i2srx_data0 11 mi2stx_ws0 12 mi2stx_bck0 13 mi2stx_data0 14 tck - - - - row n 1 usb_gnda 2 usb_dm 3 mlcd_db_15 4 mlcd_db_11 5 mlcd_db_8 6 mlcd_db_2 7 mlcd_db_4 8 mlcd_db_0 9 mlcd_rw_wr 10 i2srx_bck0 11 jtagsel 12 uart_txd 13 muart_cts_n 14 mi2stx_clk0 - - - - table 3. pin allocation table ?continued pin symbol pin symbol pin symbol pin symbol
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 6 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers row p 1 usb_vdda33 2 usb_dp 3 mlcd_db_14 4 mlcd_db_13 5 mlcd_db_7 6 mlcd_db_3 7 mlcd_db_5 8 mlcd_rs 9 mlcd_db_1 10 tms 11 i2srx_ws0 12 uart_rxd 13 trst_n 14 muart_rts_n - - - - table 3. pin allocation table ?continued pin symbol pin symbol pin symbol pin symbol table 4. pin description pin names with prefix m are multiplexed pins. see table 10 for pin function selection of multiplexed pins. pin name bga ball digital i/o level [1] application function pin state after reset cell type [2] description clock generation unit ffast_in a10 sup1 ai - aio2 12 mhz oscillat or clock input ffast_out b10 sup1 ao aio2 12 mhz oscillat or clock output vdda12 d11; e10 sup1 supply ps3 12 mhz oscillator/plls analog supply vssa12 e9 ground - cg1 12 mhz oscillator/plls analog ground rstin_n h14 sup3 di i dio2 system reset input (active low) clk_256fs_o h12 sup3 do o dio1 programmable clock output; fractionally der ived from clk1024fs_base clock domain. generally used for audio codec master clock. clock_out j4 sup3 do o dio1 programmable clock output; fractionally der ived from sys_base clock domain. sysclk_o [3] g13 sup3 do o dio1 programmable clock output. output one of seven base/reference input clocks. no fractional divider. 10-bit adc adc10b_vdda33 a13 sup3 supply - ps3 10-bit adc analog supply adc10b_gnda a12 ground - cg1 10-bit adc analog ground adc10b_gpa0 b14 sup3 ai - aio1 10-bit adc analog input adc10b_gpa1 a14 sup3 ai - aio1 10-bit adc analog input adc10b_gpa2 b13 sup3 ai - aio1 10-bit adc analog input adc10b_gpa3 c14 sup3 ai - aio1 10-bit adc analog input usb hs 2.0 otg usb_vbus l2 sup5 ai - aio3 usb supply detection line usb_id m1 sup3 ai - aio1 indicates to the usb transceiver whether in de vice (usb_id high) or host (usb_id low) mode (contains internal pull-up resistor) usb_rref j5 sup3 aio - aio1 usb connection for external reference resistor (12 k 1 %) to analog ground supply usb_dp p2 sup3 aio - aio1 usb d+ connection with integrated 45 terminatio n resistor usb_dm n2 sup3 aio - aio1 usb d ? conne ction with integrated 45 terminatio n resistor
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 7 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers usb_vdda12_pll l1 sup1 supply - ps3 usb pll supply usb_vdda33_drv m2 sup3 supply - ps3 usb analog supply for driver usb_vdda33 p1 sup3 supply - ps3 usb analog supply for phy usb_vssa_term l3 ground - cg1 usb analog ground for clean reference for on chip termination resistors usb_gnda n1 ground - cg1 usb analog ground usb_vssa_ref k4 ground - cg1 usb analog ground for clean reference jtag jtagsel n11 sup3 di i dio1 jtag selection. controls output function of scan_t do and arm_tdo signals. tdi k9 sup3 di i dio1 jtag data input trst_n p13 sup3 di i dio1 jtag reset input tck m14 sup3 di i dio1 jtag clock input tms p10 sup3 di i dio1 jtag mode select input scan_tdo f10 sup3 do o/z dio1 jtag tdo signal from scan t ap controller. pin state is contro lled by jtagsel. arm_tdo e11 sup3 do o dio1 jtag tdo signal from arm926 tap control ler. buf_trst_n f11 sup3 do o dio1 buffered trst_n out signal. used for conn ecting an on board tap controller (fpga, dsp, etc.). buf_tck d13 sup3 do o dio1 buffered tck out signal. used for connecting an on board tap controller (fpga, dsp, etc.). buf_tms d14 sup3 do o dio1 buffered tms out signal. used for connecting an on board tap controller (fpga, dsp, etc.). uart muart_cts_n [3] [4] n13 sup3 di / gpio i dio1 uart clear to send (active low) muart_rts_n [3] [4] p14 sup3 do / gpio o dio1 uart ready to send (active low) uart_rxd [3] p12 sup3 di / gpio i dio1 uart serial input uart_txd [3] n12 sup3 do / gpio o dio1 uart serial output i 2 c master/slave interface i2c_sda0 c10 sup3 dio i iicd i 2 c data line i2c_scl0 d10 sup3 dio i iicc i 2 c clock line i2c_sda1 [3] e12 sup3 dio o dio1 i 2 c data line i2c_scl1 [3] e13 sup3 dio o dio1 i 2 c clock line serial peripheral interface spi_cs_out0 [3] a7 sup3 do o dio4 spi chip select output (master) spi_sck [3] a8 sup3 dio i dio4 spi clock input (sla ve) / clock output (master) spi_miso [3] c8 sup3 dio i dio4 spi data input (master) / data output (slave) table 4. pin description pin names with prefix m are multiplexed pins. see table 10 for pin function selection of multiplexed pins. pin name bga ball digital i/o level [1] application function pin state after reset cell type [2] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 8 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers spi_mosi [3] b7 sup3 dio i dio4 spi data output (master) / data input (slave) spi_cs_in [3] b8 sup3 di i dio4 spi chip select input (slave) digital power supply vddi h3; l7 ; l12; c12; c6; a9; c9 sup1 supply - cs2 digital core supply vssi a11; c7 ; d12; g4; l6; l11 ground - cg2 digital core ground peripheral power supply vdde_ioa b2; e5; f5 ; g5; h5 sup4 supply - ps1 peripheral supply for nand flash interface vdde_iob l4; m5; m7; m9 sup8 supply - ps1 peripheral supply for sdram/lcd vdde_ioc c13; d5 ; d7; e8; g12; l10; k11 sup3 supply - ps1 peripheral supply vsse_ioa c3; c4 ; e4; f4; h4; k3 ground - pg1 vsse_iob m3; m4; m6; m8 ground - pg1 table 4. pin description pin names with prefix m are multiplexed pins. see table 10 for pin function selection of multiplexed pins. pin name bga ball digital i/o level [1] application function pin state after reset cell type [2] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 9 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers vsse_ioc b12; d6 ; d8; d9; g11; l9; l13 ground - pg1 lcd interface mlcd_csb [3] k8 sup8 do o dio4 lcd chip select (active low) mlcd_e_rd [3] l8 sup8 do o dio4 lcd, 6800 enable, 8080 read enable (active high ) mlcd_rs [3] p8 sup8 do o dio4 lcd, instruction register (low)/ data register (high) select mlcd_rw_wr [3] n9 sup8 do o dio4 lcd, 6800 read/write select, 8080 write enab le (active high) mlcd_db_0 [3] n8 sup8 dio o dio4 lcd data 0 mlcd_db_1 [3] p9 sup8 dio o dio4 lcd data 1 mlcd_db_2 [3] n6 sup8 dio o dio4 lcd data 2 mlcd_db_3 [3] p6 sup8 dio o dio4 lcd data 3 mlcd_db_4 [3] n7 sup8 dio o dio4 lcd data 4 mlcd_db_5 [3] p7 sup8 dio o dio4 lcd data 5 mlcd_db_6 [3] k6 sup8 dio o dio4 lcd data 6 mlcd_db_7 [3] p5 sup8 dio o dio4 lcd data 7 mlcd_db_8 [3] n5 sup8 dio o dio4 lcd data 8 / 8-bit data 0 mlcd_db_9 [3] l5 sup8 dio o dio4 lcd data 9 / 8-bit data 1 mlcd_db_10 [3] k7 sup8 dio o dio4 lcd data 10 / 8-bit data 2 mlcd_db_11 [3] n4 sup8 dio o dio4 lcd data 11 / 8-bit data 3 mlcd_db_12 [3] k5 sup8 dio o dio4 lcd data 12 / 8-bit data 4 / 4-bit data 0 mlcd_db_13 [3] p4 sup8 dio o dio4 lcd data 13 / 8-bit data 5 / 4-bit data 1 / se rial clock output mlcd_db_14 [3] p3 sup8 dio o dio4 lcd data 14 / 8-bit data 6 / 4-bit data 2 / se rial data input mlcd_db_15 [3] n3 sup8 dio o dio4 lcd data 15 / 8-bit data 7 / 4-bit data 3 / serial dat a output table 4. pin description pin names with prefix m are multiplexed pins. see table 10 for pin function selection of multiplexed pins. pin name bga ball digital i/o level [1] application function pin state after reset cell type [2] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 10 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers i 2 s/digital audio input i2srx_data0 [3] m10 sup3 di / gpio i dio1 i 2 s serial data receive input i2srx_data1 [3] g14 sup3 di / gpio i dio1 i 2 s serial data receive input i2srx_bck0 [3] n10 sup3 dio / gpio i dio1 i 2 s bitclock i2srx_bck1 [3] f14 sup3 dio / gpio i dio1 i 2 s bitclock i2srx_ws0 [3] p11 sup3 dio / gpio i dio1 i 2 s word select i2srx_ws1 [3] f13 sup3 dio / gpio i dio1 i 2 s word select i 2 s/digital audio output mi2stx_data0 [3] m13 sup3 do / gpio o dio1 i 2 s serial data transmit output mi2stx_bck0 [3] m12 sup3 do / gpio o dio1 i 2 s bitclock mi2stx_ws0 [3] m11 sup3 do / gpio o dio1 i 2 s word select mi2stx_clk0 [3] n14 sup3 do / gpio o dio1 i 2 s serial clock i2stx_data1 [3] f12 sup3 do / gpio o dio1 i 2 s serial data transmit output i2stx_bck1 [3] e14 sup3 do / gpio o dio1 i 2 s bitclock i2stx_ws1 [3] g10 sup3 do / gpio o dio1 i 2 s word select general purpose i/o (ioconfig module) gpio0 k10 sup3 gpio i dio1 general purpose i/o pin 0 (mode pin 0) gpio1 j10 sup3 gpio i dio1 general purpose i/o pin 1 (mode pin 1) gpio2 l14 sup3 gpio i dio1 general purpose i/o pin 2 (mode pin 2) gpio3 b11 sup3 gpio i dio1 general purpose i/o pin 3 gpio4 c11 sup3 gpi i dio1 general purpose input pin 4 mgpio5 [3] b6 sup3 gpio i dio4 general purpose i/o pin 5 mgpio6 [3] a6 sup3 gpio i dio4 general purpose i/o pin 6 mgpio7 [3] a5 sup3 gpio i dio4 general purpose i/o pin 7 mgpio8 [3] b5 sup3 gpio i dio4 general purpose i/o pin 8 mgpio9 [3] c5 sup3 gpio i dio4 general purpose i/o pin 9 mgpio10 [3] a4 sup3 gpio i dio4 general purpose i/o pin 10 gpio11 h13 sup3 gpio i dio1 general purpose i/o pin 11 gpio12 h10 sup3 gpio i dio1 general purpose i/o pin 12 gpio13 j12 sup3 gpio i dio1 general purpose i/o pin 13 gpio14 j14 sup3 gpio i dio1 general purpose i/o pin 14 gpio15 j13 sup3 gpio i dio1 general purpose i/o pin 15 gpio16 j11 sup3 gpio i dio1 general purpose i/o pin 16 gpio17 k12 sup3 gpio i dio1 general purpose i/o pin 17 gpio18 k14 sup3 gpio i dio1 general purpose i/o pin 18 gpio19 h11 sup3 gpio i dio1 general purpose i/o pin 19 gpio20 k13 sup3 gpio i dio1 general purpose i/o pin 20 table 4. pin description pin names with prefix m are multiplexed pins. see table 10 for pin function selection of multiplexed pins. pin name bga ball digital i/o level [1] application function pin state after reset cell type [2] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 11 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers [1] digital i/o levels are explained in ta b l e 5 . [2] cell types are explained in table 6 . [3] pin can be configured as gpio pin in the ioconfig block. [4] the uart flow control lines (muart_cts_n and muart_rts_n) are multiplexed. this means that if these balls are not required f or uart flow control, they can also be selected to be used for an alternative function: spi chip select signals (spi_cs_out1 and spi_cs_out2) external bus interface (nand flash controller) ebi_a_0_ale [3] b3 sup4 do o dio4 ebi address latch enable ebi_a_1_cle [3] a2 sup4 do o dio4 ebi command latch enable ebi_d_0 [3] g2 sup4 dio i dio4 ebi data i/o 0 ebi_d_1 [3] f2 sup4 dio i dio4 ebi data i/o 1 ebi_d_2 [3] f1 sup4 dio i dio4 ebi data i/o 2 ebi_d_3 [3] e1 sup4 dio i dio4 ebi data i/o 3 ebi_d_4 [3] e2 sup4 dio i dio4 ebi data i/o 4 ebi_d_5 [3] d1 sup4 dio i dio4 ebi data i/o 5 ebi_d_6 [3] d2 sup4 dio i dio4 ebi data i/o 6 ebi_d_7 [3] c1 sup4 dio i dio4 ebi data i/o 7 ebi_d_8 [3] b1 sup4 dio i dio4 ebi data i/o 8 ebi_d_9 [3] a3 sup4 dio i dio4 ebi data i/o 9 ebi_d_10 [3] a1 sup4 dio i dio4 ebi data i/o 10 ebi_d_11 [3] c2 sup4 dio i dio4 ebi data i/o 11 ebi_d_12 [3] g3 sup4 dio i dio4 ebi data i/o 12 ebi_d_13 [3] d3 sup4 dio i dio4 ebi data i/o 13 ebi_d_14 [3] e3 sup4 dio i dio4 ebi data i/o 14 ebi_d_15 [3] f3 sup4 dio i dio4 ebi data i/o 15 ebi_dqm_0_noe [3] h1 sup4 do o dio4 nand read enable (active low) ebi_nwe [3] j2 sup4 do o dio4 nand write enable (active low) nand_ncs_0 [3] j1 sup4 do o dio4 nand chip enable 0 nand_ncs_1 [3] j3 sup4 do o dio4 nand chip enable 1 nand_ncs_2 [3] k1 sup4 do o dio4 nand chip enable 2 nand_ncs_3 [3] k2 sup4 do o dio4 nand chip enable 3 mnand_rybn0 [3] e6 sup4 di i dio4 nand ready/busy 0 mnand_rybn1 [3] e7 sup4 di i dio4 nand ready/busy 1 mnand_rybn2 [3] b4 sup4 di i dio4 nand ready/busy 2 mnand_rybn3 [3] d4 sup4 di i dio4 nand ready/busy 3 ebi_ncas_blout_0 [3] g1 sup4 do o dio4 ebi lower lane byte select (7:0) ebi_nras_blout_1 [3] h2 sup4 do o dio4 ebi upper lane byte select (15:8) pulse width modulation module pwm_data [3] b9 sup3 do / gpio o dio1 pwm output table 4. pin description pin names with prefix m are multiplexed pins. see table 10 for pin function selection of multiplexed pins. pin name bga ball digital i/o level [1] application function pin state after reset cell type [2] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 12 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers [1] when the sdram is used, the supply voltage of the nand flash, s dram, and the lcd interface must be the same, i.e. sup4 and sup8 should be connected to the same rail. (see also section 6.26.3 .) 6. functional description 6.1 arm926ej-s the processor embedded in the LPC3130/3131 is the arm926ej-s. it is a member of the arm9 family of general-purpose microprocessors. the arm926ej-s is intended for multi-tasking applications where full memory management, high performance, and low power are important. table 5. supply domains supply domain voltage range related supply pins description sup1 1.0 v? 1.3 v vddi, vdda12, usb_vdda12_pll, digital core supply sup3 2.7 v - 3.3 v vdde_ioc, adc10b_vdda33, usb_vdda33_dr v, usb_vdda33, peripheral supply sup4 1.65 v - 1.95 v (in 1.8 v mode) 2.5 v - 3.1 v (in 2.8 v mode) vdde_ioa peripheral supply for nand flash interface sup5 4.5 v? 5.5 v usb_vbus usb vbus voltage sup8 1.65 v - 1.95 v (in 1.8 v mode) 2.5 v - 3.1 v (in 2.8 v mode) vdde_iob peripheral supply for sdram/sr am/bus-based lcd [1] table 6: i/o pads cell type pad type function description dio1 bspts3chp digital input/output bidirectional 3.3 v; 3-state output; 3 ns slew rate control; plain inp ut; cmos with hysteresis; programmable pull-up, pull-down, repeater dio2 bpts5pcph digital input/output bidirectional 5 v; plain input; 3-state output; cmos with prog rammable hysteresis; programmable pull-up, pull-down, repeater dio4 mem1 bsptz40pchp digital input/output bidirectional 1.8 v or 2.8 v; plain input; 3-state output; prog rammable hysteresis; programmable pull-up, pull-down, repeater iicc iic3m4scl digital input/output i 2 c-bus; clock signal iicd iic3mvsda digital input/output i 2 c-bus; data signal aio1 apio3v3 analog input/output analog input/output; protection to external 3.3 v supply rail aio2 apio analog input/output analog input/output aio3 apiot5v analog input/output analog input/output; 5 v toler ant p ad-based esd protection cs1 vddco core supply - cs2 vddi core supply - ps1 vdde3v3 peripheral supply - ps2 vdde peripheral supply - cg1 vssco core ground - cg2 vssis core ground - pg1 vsse peripheral ground -
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 13 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers this module has the following features: ? arm926ej-s processor core which uses a fi ve-stage pipeline consisting of fetch, decode, execute, memory, and write stages. the processor supports both the 32-bit arm and 16-bit thumb instruction sets, which allows a trade off between high performance and high code density. the arm926ej-s also executes an extended armv5te instruction set which includes support for java byte code execution. ? contains an amba biu for both data accesses and instruction fetches. ? memory management unit (mmu). ? 16 kb instruction and 16 kb data separate cache memories with an 8 word line length. the caches are organized us ing harvard architecture. ? little endian is supported. ? the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debugging. ? supports dynamic clock gating for power reduction. ? the processor core clock can be set equal to the ahb bus clock or to an integer number times the ahb bus clock. the pr ocessor can be switched dynamically between these settings. ? arm stall support.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 14 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.2 memory map (1) lpc3131 only. fig 3. LPC3130/3131 memory map 0x0000 0000 0x0000 1000 0 gb 2 gb 4 gb 0x1102 8000 0x1104 0000 0x1105 8000 0x1200 0000 0x1201 0000 0x1300 0000 0x1300 8000 0x1300 b000 0x1500 0000 0x1600 0000 reserved 96 kb isram0 96 kb isram1 (1) 128 kb isrom reserved reserved reserved reserved external sram bank 0 external sram bank 1 external sdram bank 0 reserved reserved apb0 domain apb1 domain apb2 domain apb3 domain 0x1700 0000 0x1700 8000 0x1700 9000 0x1800 0000 0x1800 0900 0x1900 0000 0x1900 1000 0x2000 0000 0x2002 0000 0x2004 0000 0x3000 0000 0x4000 0000 0x6000 0000 0x6000 1000 0x7000 0000 0x7000 0800 0x8000 0000 0xffff ffff reserved mci/sd/sdio usb otg apb4 domain mpmc configuration registers shadow area LPC3130/3131 interrupt controller nand buffer reserved reserved 0x1300 2000 0x1300 2400 0x1300 0000 event router adc 10 bit 0x1300 2800 0x1300 3000 0x1300 4000 0x1300 6000 0x1300 5000 sysconfig register ioconfig cgu apb0 domain 0x1500 0400 0x1500 0000 pcm reserved lcd 0x1500 0800 0x1500 1000 0x1500 2000 0x1600 0000 0x1500 3000 reserved uart spi apb2 domain 0x1700 0800 0x1700 0000 dma nand flash controller 0x1700 1000 0x1700 8000 reserved apb4 domain reserved 0x1600 0080 apb3 domain 0x1300 8400 0x1300 8000 timer 0 timer 1 0x1300 8800 0x1300 8c00 0x1300 9000 0x1300 a400 0x1300 b000 0x1300 a000 timer 2 timer 3 pwm i2c0 i2c1 apb1 domain reserved 002aae125 i2s system config 0x1600 0100 i2stx_0 0x1600 0180 i2stx_1 0x1600 0200 i2srx_0 0x1600 0280 i2srx_1 wdt reserved rng
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 15 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.3 jtag the joint test action group (jtag) interface allows the incorporation of the LPC3130/3131 in a jtag scan chain. this module has the following features: ? arm926 debug access ? boundary scan 6.4 nand flash controller the nand flash controller is used as a dedi cated interface to nand flash devices. figure 4 shows a block diagram of the nand flash controller module. the heart of the module is formed by a controller block that co ntrols the flow of data from/to the ahb bus through the nand flash controller block to/fr om the (external) nand flash. an error correction encoder/decoder (ecc enc/dec) mo dule allows for hardware error correction for support of multi-level ce ll (mlc) nand flash devices. before data is written from the buf fer to the nand flash, optionally it is first protected by an error correction code generated by the ecc module. after data is read from the nand flash, the error correction module corrects any errors. this module has the following features: ? dedicated nand flash interface with hard ware controlled read and write accesses. ? wear leveling support with 516 byte mode. ? software controlled command and address transfers to support wide range of flash devices. fig 4. block diagram of the nand flash controller 002aae127 ahb multilayer matrix buffer controller ecc encoder/ decoder nand interface dma transfer request
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 16 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? software control mode where the arm is directly master of the flash device. ? support for 8 bit and 16 bit flash devices. ? support for any page size from 0.5 kb upwards. ? programmable nand flash timing parameters. ? support for up to 4 nand devices. ? error correction module (ecc) for mlc nand flash support: ? ree d-solomon error correction encoding and decoding. ? use s reed-solomon code words with 9-bit symbols over gf(2 9 ), a total codeword length of 469 symbols, including 10 pa rity symbols, giving a minimum hamming distance of 11. ? up to 8 symbol errors can be corrected per codeword. ? er ror correction can be turned on and off to match the demands of the application. ? pa rity generator for error correction encoding. ? w ear leveling information can be integrated into protected data. ? in terrupts generated after completion of error correction task with 3 interrupt registers. ? error correc tion statistics distribu ted to arm using interrupt scheme. ? interface is compatible with the arm external bus interface (ebi). 6.5 multi-port memory controller (mpmc) the multi-port memory controller supports the interface to different memory types, for example: ? sdram ? low-power sdram ? static memory interface this module has the following features: ? dynamic memory interface support incl uding sdram, jedec low-power sdram. ? address line supporting up to 128 mb of dynamic memory. ? the mpmc has two ahb interfaces: a. an interface for accessing external memory. b. a separate control interface to program the mpmc. this enables the mpmc re gisters to be situated in memory wit h other system peripheral registers. ? low transaction latency. ? read and write buffers to reduce latency an d to improve performance, particularly for un-cached processors. ? static memory features include: ? a synchronous page mode read ? p rogrammable wait states ? b us turnaround delay ? o utput enable and write enable delays
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 17 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? extended wait ? one chip select for synchronous memory and two chip selects for static memory devices. ? power-saving modes. ? dynamic memory self-refresh mode supported. ? controller support for 2 k, 4 k, and 8 k row address synchronous memory parts. ? support for all ahb burst types. ? little and big-endian support. ? support for the external bus interface (ebi) that enables the memory controller pads to be shared. 6.6 external bus interface (ebi) the ebi module acts as multiplexer with ar bitration between the nand flash and the sdram/sram memory modules connected externally through the mpmc. the main purpose for using the ebi module is to save external pins. however only data and address pins are multiplexed. control signals towards and from the external memory devices are not multiplexed. 6.7 internal rom memory the internal rom memory is used to store the boot code of the LPC3130/3131. after a reset, the arm processor will start its code execution from this memory. the LPC3130/3131 rom memory has the following features: ? supports booting from spi flash, nand flash, sd/sdhc/mmc cards, uart, and usb (dfu class) interfaces. ? supports option to perform crc32 checking on the boot image. ? supports booting from managed nand devices such as movinand, inand, emmc-nand and esd-nand using sd/mmc boot mode. ? contains pre-defined mmu table (16 kb) for simple systems. the boot rom determines the boot mode ba se d on reset state of gpio0, gpio1, and gpio2 pins. ta b l e 8 shows the various boot modes supported on the LPC3130/3131: table 7. memory map of the ext ernal sram/sdram memory modules module maximum address space data width device size external sram0 0x2000 0000 0x2000 ffff 8 bit 64 kb 0x2000 0000 0x2001 ffff 16 bit 128 kb external sram1 0x2002 0000 0x2002 ffff 8 bit 64 kb 0x2002 0000 0x2003 ffff 16 bit 128 kb external sdram0 0x3000 0000 0x37ff ffff 16 bit 128 mb
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 18 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.8 internal ram memory the isram (internal static ram memory) contro ller module is used as controller between the ahb bus and the internal ram memory. the internal ram memory can be used as working memory for the arm processor and as temporary storage to execute the code that is loaded by boot rom from external devices such as spi-flash, nand flash, and sd/mmc cards. this module has the following features: ? capacity of 96 kb (LPC3130) or 192 kb (lpc3131) ? on lpc3131 implemented as two independent 96 kb memory banks 6.9 memory card interface (mci) the mci controller interface can be used to access memory cards according to the secure digital (sd) and multi-media card (mmc) standards. the host controller can be used to interface to small form factor expansion cards compliant to the sdio card standard as well. finally, the mci supports ce-ata 1.1 compliant hard disk drives. this module has the following features: ? one 8-bit wide interface. ? supports high-speed sd, versions 1.01, 1.10 and 2.0. ? supports sdio version 1.10. ? supports mmcplus, mmcmobile and mmcmicro cards based on mmc 4.1. ? supports sdhc memory cards. ? crc generation and checking. table 8. LPC3130/3131 boot modes boot mode gpio0 gpio1 gpio2 description nand 0 0 0 boots from nand flash. if proper image is not found, b oot rom will switch to dfu boot mode. spi 0 0 1 boot from spi nor flash con nected to spi_cs_out0. if proper image is not found, boot rom will switch to dfu boot mode. dfu 0 1 0 device boots via usb using dfu class specification. sd/mmc 0 1 1 boot rom searches all the partitions on the sd /mmc/sdhc/mmc+/emmc/es d card for boot image. if partition table is missing, it will start searching from sector 0. a valid image is said to be found if a valid image header is found, followed by a valid image. if a proper image is not found, boot rom will switch to dfu boot mode. reserved 0 1 0 0 reserved for testing. nor flash 1 0 1 boot from parallel nor flash connected to ebi_nstcs_1. uart 1 1 0 boot rom tries to download boot image from uart ((1 15200 ? 8 ? n -1) assuming 12 mhz ffast clock). te s t 1 1 1 boot rom is testing isram usi ng memory pattern test. after test switches to uart boot mode.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 19 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? supports 1/4-bit sd cards. ? card detection and write protection. ? fifo buffers of 16 bytes deep. ? host pull-up control. ? sdio suspend and resume. ? 1 to 65 535 bytes blocks. ? suspend and resume operations. ? sdio read-wait. ? maximum clock speed of 52 mhz (mmc 4.1). ? supports ce-ata 1.1: ? 8 b it data width ? inc luding ata module 6.10 high-speed universal seri al bus 2.0 on-the-go (otg) the usb otg module allows the LPC3130/3131 to connect directly to a usb host such as a pc (in device mode) or to a usb device in host mode. in addition, the LPC3130/3131 has a special, built-in mode in which it en umerates as a device firmware upgrade (dfu) class, which allows for a (factory) down load of the device firmware through usb. this module has the following features: ? complies with universal serial bus specification 2.0 . ? complies with usb on-the-go supplement . ? complies with enhanced host controller interface specification . ? supports auto usb 2.0 mode discovery. ? supports all high-speed usb-compliant peripherals. ? supports all full-speed usb-compliant peripherals. ? supports software host ne gotiation protocol (hnp) an d session request protocol (srp) for otg peripherals. ? contains utmi+ compliant transceiver (phy). ? supports interrupts. ? this module has its own, integrated dma engine. 6.11 dma controller the dma controller can perform dma transfers on the ahb bus without using the cpu. this module has the following features: ? supported transfer types: memory to memory: ? m emory can be copied from the source address to the destination address with a specified length, while incrementing the address for both the source and destination. memory to peripheral:
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 20 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? data is transferred from incrementing memory to a fixed address of a peripheral. the flow is controlled by the peripheral. peripheral to memory: ? da ta is transferred from a fixed address of a peripheral to incrementing memory. the flow is controlled by the peripheral. ? supports single data transfers for all transfer types. ? supports burst transfers for memory to memory transfers. a burst always consists of multiples of 4 (32 bit) words. ? the dma controller has 12 channels. ? scatter-gather is used to gather data lo cated at different areas of memory. two channels are needed per scatter-gather action. ? supports byte, half word and word transfers, and correctly aligns it over the ahb bus. ? compatible with arm flow control for sing le requests (sreq), last single requests (lsreq), terminal count info (tc), and dma clearing (clr). ? supports swapping in endianess of the transported data. 6.12 interrupt controller (intc) the interrupt controller collects interrupt requests from multip le devices, masks interrupt requests, and forwards the combined requests to the processor. the interrupt controller also provides facilities to identify the in terrupt requesting devices to be served. this module has the following features: ? the interrupt controller decodes all the interrupt requests issued by the on-chip peripherals. ? two interrupt lines (fast interrupt request (f iq), interrupt reques t (irq)) to the arm core. the arm core supports two distinct leve ls of priority on all interrupt sources, fiq for high priority interrupts and irq for normal priority interrupts. ? software interrupt request capability associated with each request input. ? visibility of the interrupt?s request state before masking. ? support for nesting of interrupt service routines. ? interrupts routed to irq and to fiq are vectored. table 9: peripherals that support dma access peripheral name supported transfer types nand flash controller memory to memory spi memory to peripheral and peripheral to memory mci memory to peripheral and peripheral to memory lcd interface memory to peripheral uart memory to peripheral and peripheral to memory i2c0/1-bus master/slave memory to peripheral and peripheral to memory i2s0/1 receive peripheral to memory i2s0/1 transmit memory to peripheral pcm interface memory to peripheral and peripheral to memory
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 21 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? level interrupt support. the following blocks can generate interrupts: ? nand flash controller ? usb 2.0 high-speed otg ? event router ? 10-bit adc ? uart ? lcd ? mci ? spi ? i2c0 and i2c1 controllers ? timer0, timer1, timer2, and timer3 ? i 2 s transmit: i2stx_0 and i2stx_1 ? i 2 s receive: i2srx_0 and i2srx_1 ? dma 6.13 multi-layer ahb the multi-layer ahb is an in terconnection scheme based on the ahb protocol that enables parallel access paths between multiple masters and slaves in a system. multiple masters can have access to different slaves at the same time. figure 5 gives an overview of the multi-layer ahb configuration in the LPC3130/3131. ahb masters and slaves are numbered according to their ahb port number.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 22 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers this module has the following features: (1) lpc3131 only. fig 5. LPC3130/3131 multi-layer ahb matrix connections masters = master/slave connection supported by matrix 002aae126 usb-otg ahb master 3 0 dma 2 i-cache d-cache 1 arm 926ej-s ahb-apb bridge 0 ahb-apb bridge 1 ahb-apb bridge 3 ahb-apb bridge 4 nand controller interrupt controller pwm i2c0 i2c0 timer 0 10-bit adc cgu wdt system control ioconfig event router i2s0/1 nand registers dma registers timer 1 timer 2 timer 3 ahb-apb bridge 2 uart lcd spi pcm slaves ahb multilayer matrix 0 1 2 3 4 5 mci sd/sdio 7 usb high-speed otg 8 isram 0 9 isram 1 (1) 10 isrom 11 mpmc config mpmc controller 13 12 6 0 0 123 0123 5 rng 64 01 23456 01 buffer asynchronous bridge asynchronous bridge asynchronous bridge asynchronous bridge synchronous bridge
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 23 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix). ? round-robin priority mechanism for bus arbitr ation: all masters have the same priority and get bus access in their natural order ? four devices on a master port (listed in their natural order for bus arbitration): ? dma ? arm9 26 instruction port ? arm9 26 data port ? usb otg ? devices on a slave port (some ports ar e shared between mu ltiple devices): ? ahb to apb bridge 0 ? ahb to apb bridge 1 ? ahb to apb bridge 2 ? ahb to apb bridge 3 ? ahb to apb bridge 4 ? in terrupt controller ? nand flash controller ? mc i sd/sdio ? usb 2.0 hig h-speed otg ? 96 kb isram ? 9 6 kb isram (lpc3131 only) ? 12 8 kb rom ? mpm c 6.14 apb bridge the apb bridge is a bus bridge between the amba advanced high-performance bus (ahb) and the arm peripheral bus (apb) interface. the module supports two different architectures: ? single-clock architecture, synchronous bridge. the same clock is used at the ahb side and at the apb side of the bridge . the ahb-to-apb4 br idge uses this architecture. ? dual-clock architecture, asynchronous bridge. different clocks are used at the ahb side and at the apb side of the br idge. the ahb-to- apb0, ahb-to-apb1, ahb-to-apb2, and ahb-to-apb3 br idges use this architecture. 6.15 clock generation unit (cgu) the clock generation unit generates all clock si gnals in the system and controls the reset signals for all modules. the stru cture of the cgu is shown in figure 6 . each output clock generated by the cgu belongs to one of the do mains. each clock domain is fed by a single base clock that originates from one of the available clock sources. within a clock domain, fractional dividers are available to divide the base clock to a lower frequency.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 24 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers within most clock domains, the output clocks are again grouped into one or more subdomains. all output clocks within one subdom ain are either all generated by the same fractional divider or they are connected dire ctly to the base clock. therefore all output clocks within one subdomain have the same frequency and all output clocks within one clock domain are synchronous because they originate from the same base clock. the cgu reference clock is generated by the exte rnal crystal. in addition, the cgu has several phase locked loop (pll) circuits to g enerate clock signals that can be used for system clocks and/or audio clocks. all clock so urces, except the output of the plls, can be used as reference input for the plls. this module has the following features: ? advanced features to optimize the system for low power: ? all ou tput clocks can be disabled indivi dually for flexible power optimization. ? so me modules have automatic clock gating. they are only active when bus access to the module is required. ? v ariable clock scaling for au tomatic power optimization of the ahb bus (high clock frequency when the bus is active, low clock frequency when the bus is idle). ? clo ck wake-up feature: module clocks can be programmed to be activated automatically on the basis of an event detected by the event router (see also section 6.19 ). for example, all clocks (including the arm /bus clocks) are off and activated automatically when a button is pressed. ? supports five clock sources: ? reference c lock ge nerated by the oscillator with an external crystal. ? pins i2srx_bck0, i2srx_w s 0, i2srx_bck1 and i2srx_ws1 are used to input external clock signals (used for generating audio frequencies in i2srx slave mode, see also section 6.4 ). ? supports two plls: ? syste m pll generates programmable system clock frequency from its reference input. ? i 2 s pll generates programmable audio clock frequency (typically 256 fs) from its reference input. remark: bo th the system pll and the i 2 s pll generate their frequencies based on their (individual) reference clocks. the reference clocks can be programmed to the oscillator clock or one of the external clock signals. ? highly flexible switchbox to distribute the signals from the clock sources to the module clocks: ? ea ch clock generated by the cgu is derived from one of the base clocks and optionally divided by a fractional divider. ? ea ch base clock can be programmed to have any one of the clock sources as an input clock. ? f ractional dividers can be used to divide a base clock by a fractional number to a lower clock frequency. ? f ractional dividers support clock stretching to obtain a (near) 50 % duty cycle output clock. ? register interface to reset all modules un der software control.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 25 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? based on the input of the watchdog timer (see also section 6.16 ), the cgu can generate a system-wide reset in the case of a sy stem stall. 6.16 watchdog timer (wdt) the watchdog timer can be used to generate a system reset if there is a cpu/software crash. in addition, the watchdog timer can be used as an ordinary timer. figure 7 shows how the watchdog timer module is connected in the system. this module has the following features: ? in the event of a software or hardware failure, generates a chip-wide reset request when its programmed time-out period has expired (output m1). ? watchdog counter can be reset by a periodical software trigger. ? after a reset, a regist er will indicate whether a rese t has occurred because of a watchdog generated reset. ? watchdog timer can also be used as a normal timer (output m0). the LPC3130/3131 has 11 clock domains (n = 11). the num ber of fractional dividers m depends on the clock domain. fig 6. cgu block diagram oscillator i2srx_bck0 i2srx_ws0 i2srx_bck1 i2srx_ws1 base i 2 s/audio pll external crystal system pll 002aae085 clock domain 0 clock domain n fractional divider 0 fractional divider m clock resources clock outputs switchbox subdomain clocks to modules
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 26 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.17 input/output configur ation module (ioconfig) the general purpose input/output (gpio) pins can be controlled through the register interface provided in the ioconfig module. next to several dedica ted gpio pins, most digital i/o pins can also be used as gpio if they are not required for their normal, dedicated function. this module has the following features: ? provides control for the digital pins that can double as gpio (next to their normal function). the pinning list in ta b l e 4 indicates which pins can double as gpio. ? each pin controlled by the ioconfig can be configured for four operational modes: ? no rmal operation (i.e. controlled by a function block). ? driv en low. ? driv en high. ? hig h impedance/input. ? the gpio pins can be observed (read) in any mode. ? the register interface provides set and clear access methods for choosing the operational mode. 6.18 10-bit analog-to-digit al converter (adc10b) this module is a 10-bit su ccessive approximation analog-to-digital converter (adc) with an input multiplexer to allow fo r multiple analog signals on it s input. a common use of this module is to read out multiple keys on one input from a resistor network. this module has the following features: ? four analog input channels, selected by an analog multiplexer. ? programmable adc resolution from 2 bit to 10 bit. ? the maximum conversion rate is 400 ksample/s for 10 bit resolution and 1500 ksample/s for 2 bit resolution. ? single a/d conversion scan mode and continuous a/d conversion scan mode. ? power-down mode. fig 7. block diagram of the watchdog timer 002aae086 event router wdt m0 m1 cgu interrupt controller fiq irq reset apb
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 27 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.19 event router the event router extends the interrupt ca pability of the system by offering a flexible and versatile way of generating interrupts. combined with the wake-up functionality of the cgu, it also offers a way to wake up the system from suspend mode (with all clocks deactivated). the event router has four interrupt outputs connected to the interrupt controller and one wake-up output connected to the cgu as shown in figure 8 . the output signals are activated when an event (for instance a rising edge) is detected on one of the input sign als. the input signals of the event router are connected to relevant internal control signals in the system or to external signals through pins of the LPC3130/3131. this module has the following features: ? provides programmable routing of input events to multiple outputs for use as interrupts or wake up signals. ? input events can come from internal signals or from the pins that can be used as gpio. ? inputs can be used either directly or latched (edge detected) as an event source. ? the active level (polarity) of the input signal for triggering events is programmable. ? direct events will disappear when the input becomes inactive. ? latched events will remain active un til they are explicitly cleared. ? each input can be masked globally for all inputs at once. ? each input can be masked for each output individually. ? event detect status can be read for each output separately. ? event detection is fully asynchro nous (no active clock required). ? module can be used to generate a system wake-up from suspend mode. remark: all pin s that can be used as gpio ar e connected to the event router (see figure 8 ). note that they can be used to trigge r events when in normal functional mode or in gpio mode. fig 8. event router block diagram 002aae087 event router cgu interrupt controller interrupt 0 interrupt 1 interrupt 2 interrupt 3 cgu wakeup apb internal input signals external pins (gpio configurable)
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 28 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.20 random number generator the random number generator (rng) generates true random numbers for use in advanced security and digital rights management (drm) related schemes. these schemes rely upon truly random, i.e. completely unpredictable numbers. this module has the following features: ? true random number generator. ? the random number register does not rely on any kind of reset. ? the generators are free running in order to ensure randomness and security. 6.21 serial periphe ral interface (spi) the spi module is used for synchronous seri al data communication with other devices which support the spi/ssi protocol. exampl es are memories, cameras, or wifi-g. the spi/ssi-bus is a 5-wire interface, and it is suitable for low, medium, and high data rate transf ers. this module has the following features: ? supports motorola spi frame format with a word size of 8/16 bits. ? texas instruments ssi (synchronous serial interface) frame format with a word size of 4 bit to 16 bit. ? receive fifo and transmit fifo of 64 half-words each. ? serial clock rate master mode maximum 45 mhz. ? serial clock rate slave mode maximum 25 mhz. ? support for single data access dma. ? full-duplex operation. ? supports up to three slaves. ? supports maskable interrupts. ? supports dma transfers. 6.22 universal asynchronous receiver transmitter (uart) the uart module supports the industry standard serial interface. this module has the following features: ? programmable baud rate with a maximum of 1049 kbd. ? programmable data length (5 bit to 8 bit). ? implements only asynchronous uart. ? transmit break character length indication. ? programmable one to two stops bits in transmission. ? odd/even/force parity check/generation. ? frame error, overrun error and break detection. ? automatic hardware flow control. ? independent control of transmit, receive, line status, data set interrupts, and fifos.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 29 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? sir-irda encoder/decoder (from 2400 to 115 kbd). ? supports maskable interrupts. ? supports dma transfers. 6.23 pulse code modulat ion (pcm) interface the pcm interface supports the pcm and iom interfaces. the iom (isdn oriented modular) interface is primarily used to interconnect telec ommunications ics providing isdn compatib ility. it delivers a symmetrical full-duplex communication link containing user data, co ntrol/programming lines, and status channels. pcm (pulse code modulation) is a very common method used for transmitting analog da ta in digital format. most common applications of pcm are digital audio as in audio cd and computers, digital telephony and videos. this module has the following features: ? four-wire serial interface. ? can function in both master and slave modes. ? supports: ? pcm: single clocking physical format. ? m ulti-protocol (mp) pcm: configurable directional per slot. ? iom-2 : extended isdn-oriented modular. double clocking physical format. ? twelve eight bit slots in a frame with enabling control per slot. ? internal frame clock gene ration in master mode. ? receive and transmit dma handshaking using a request/clear protocol. ? interrupt generation per frame. 6.24 lcd interface the dedicated lcd interface contains logic to interface to a 6800 (motorola) or 8080 (intel) compatible lcd contro llers which support 4/8/16 bi t modes. this module also supports a serial interface mode. the speed of the interface can be adjusted in software to match the speed of the connected lcd display. this module has the following features: ? 4/8/16 bit parallel interface mode: 6800-series, 8080-series. ? serial interface mode. ? supports multiple frequencies for the 6800/8080 bus to support high- and low-speed controllers. ? supports polling the busy flag from lcd c ontroller to off-load the cpu from polling. ? contains an 16 byte fifo for sending control and data information to the lcd controller. ? supports maskable interrupts. ? supports dma transfers.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 30 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.25 i 2 c-bus master/slave interface the LPC3130/3131 contains two i 2 c master/slave interfaces. this module has the following features: ? i 2 c-bus interface 0 (i2c0) : i2c0 is a standard i 2 c-compliant bus interface with open-drain pins. this interface supports functions described in the i 2 c-bus specification for speeds up to 400 khz. th is includes multi-master operation and allows powering off this device in a working system while leaving the i 2 c-bus functional. ? i 2 c-bus interface 1 (i2c1) : i2c1 uses standard i/o pins and is intended for use with a single-master i 2 c-bus and does not support powering off of this device. standard i/os also do not support multi-master i 2 c implementations. ? supports normal mode (100 khz scl). ? fast mode (400 khz scl with 24 mhz apb clock; 325 khz with1 2 mhz apb clock; 175 khz with 6 mhz apb clock). ? interrupt support. ? supports dma transfers (single). ? four modes of operation: ? mast er transmitter ? ma ster receiver ? slav e transmitter ? slav e receiver 6.26 lcd/nand flash/ sdram multiplexing the LPC3130/3131 contains a rich set of specialized hardware interfaces but the tfbga package does not contain enough pins to allow use of all signals of all interfaces simultaneously. therefore a pin-multiplexing scheme is created, which allows the selection of the right interface for the application. pin multiplexing is enabled between the following interfaces: ? between the dedicated lcd interfac e and the external bus interface. ? between the nand flash controller and the memory card interface. ? between uart and spi. ? between i2stx_0 output and the pcm interface. the pin interface multiplexing is subd ivided into five categories: storage, video, audio, nand flash, and uart related pin multiplexi ng. each category supports several modes, which can be selected by programming the corresponding registers in the syscreg.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 31 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.26.1 pin connections table 10. pin descriptions of multiplexed pins pin name default signal alternate signal description video related pin multiplexing mlcd_csb lcd_csb ebi_nstcs_0 lcd_csb ? lcd chip select for external lcd controller. ebi_nstcs_0 ? ebi static memory chip select 0. mlcd_db_1 lcd_db_1 ebi_nstcs_1 lcd_db_1 ? lcd bidirectional data line 1. ebi_nstcs_1 ? ebi static memory chip select 1. mlcd_db_0 lcd_db_0 ebi_clkout lcd_db_0 ? lcd bidirectional data line 0. ebi_clkout ? ebi sdram clock signal. mlcd_e_rd lcd_e_rd ebi_cke lcd_e_rd ? lcd enable/read signal. ebi_cke ? ebi sdram clock enable. mlcd_rs lcd_rs ebi_ndycs lcd_rs ? lcd register select signal. ebi_ndycs ? ebi sdram chip select. mlcd_rw_wr lcd_rw_wr ebi_dqm_1 lcd_rw_wr ? lcd read write/write signal. ebi_dqm_1 ? ebi sdram data mask output 1. mlcd_db_2 lcd_db_2 ebi_a_2 lcd_db_2 ? lcd bidirectional data line 2. ebi_a_2 ? ebi address line 2. mlcd_db_3 lcd_db_3 ebi_a_3 lcd_db_3 ? lcd bidirectional data line 3. ebi_a_3 ? ebi address line 3. mlcd_db_4 lcd_db_4 ebi_a_4 lcd_db_4 ? lcd bidirectional data line 4. ebi_a_4 ? ebi address line 4. mlcd_db_5 lcd_db_5 ebi_a_5 lcd_db_5 ? lcd bidirectional data line 5. ebi_a_5 ? ebi address line 5. mlcd_db_6 lcd_db_6 ebi_a_6 lcd_db_6 ? lcd bidirectional data line 6. ebi_a_6 ? ebi address line 6. mlcd_db_7 lcd_db_7 ebi_a_7 lcd_db_7 ? lcd bidirectional data line 7. ebi_a_7 ? ebi address line 7. mlcd_db_8 lcd_db_8 ebi_a_8 lcd_db_8 ? lcd bidirectional data line 8. ebi_a_8 ? ebi address line 8. mlcd_db_9 lcd_db_9 ebi_a_9 lcd_db_9 ? lcd bidirectional data line 9. ebi_a_9 ? ebi address line 9. mlcd_db_10 lcd_db_10 ebi_a_10 lcd_db_10 ? lcd bidirectional data line 10. ebi_a_10 ? ebi address line 10. mlcd_db_11 lcd_db_11 ebi_a_11 lcd_db_11 ? lcd bidirectional data line 11. ebi_a_11 ? ebi address line 11. mlcd_db_12 lcd_db_12 ebi_a_12 lcd_db_12 ? lcd bidirectional data line 12. ebi_a_12 ? ebi address line 12. mlcd_db_13 lcd_db_13 ebi_a_13 lcd_db_13 ? lcd bidirectional data line 13. ebi_a_13 ? ebi address line 13. mlcd_db_14 lcd_db_14 ebi_a_14 lcd_db_14 ? lcd bidirectional data line 14. ebi_a_14 ? ebi address line 14.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 32 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers mlcd_db_15 lcd_db_15 ebi_a_15 lcd_db_15 ? lcd bidirectional data line 15. ebi_a_15 ? ebi address line 15. storage related pin multiplexing mgpio5 gpio5 mci_clk gpio5 ? general purpose i/o pin 5. mci_clk ? mci card clock. mgpio6 gpio6 mci_cmd gpio_6 ? general purpose i/o pin 6. mci_cmd ? mci card command input/output. mgpio7 gpio7 mci_dat_0 gpio7 ? general purpose i/o pin 7. mci_dat_0 ? mci card data input/output line 0. mgpio8 gpio8 mci_dat_1 gpio8 ? general purpose i/o pin 8. mci_dat_1 ? mci card data input/output line 1. mgpio9 gpio9 mci_dat_2 gpio9 ? general purpose i/o pin 9. mci_dat_2 ? mci card data input/output line 2. mgpio10 gpio10 mci_dat_3 gpio10 ? general purpose i/o pin 10. mci_dat_3 ? mci card data input/output line 3. nand related pin multiplexing mnand_rybn0 nand_rybn0 mci_dat_4 nand_rybn0 ? nand flash controller read/not busy signal 0. mci_dat_4 ? mci card data input/output line 4. mnand_rybn1 nand_rybn1 mci_dat_5 nand_rybn1 ? nand flash controller read/not busy signal 1. mci_dat_5 ? mci card data input/output line 5. mnand_rybn2 nand_rybn2 mci_dat_6 nand_rybn2 ? nand flash controller read/not busy signal 2. mci_dat_6 ? mci card data input/output line 6. mnand_rybn3 nand_rybn3 mci_dat7 nand_rybn3 ? nand flash controller read/not busy signal 3. mci_dat7 ? mci card data input/output line 7. audio related pin multiplexing mi2stx_data0 i2stx_data0 pcm_da i2stx_data0 ? i 2 s-bus interface 0 transmit data signal. pcm_da ? pcm serial data line a. mi2stx_bck0 i2stx_bck0 pcm_fsc i2stx_bck0 ? i 2 s-bus interface 0 transmit bitclock signal. pcm_fsc ? pcm frame synchronization signal. mi2stx_ws0 i2stx_ws0 pcm_dclk i2stx_ws0 ? i 2 s-bus interface 0 transmit word sele ct signal. pcm_dclk ? pcm data clock output. mi2stx_clk0 i2stx_clk0 pcm_db i2stx_clk0 ? i 2 s-bus interface 0 transmit clock signal. pcm_db ? pcm serial data line b. uart related pin multiplexing muart_cts_n uart_cts_n spi_cs_out1 uart_cts_n ? uart modem control clear-to-send signal. spi_cs_out1 ? spi chip select out for slave 1 (used in master mode). muart_rts_n uart_rts_n spi_cs_out2 uart_rts_n ? uart modem control request-to-send signal. spi_cs_out2 ? spi chip select out for slave 2 (used in master mode). table 10. pin descriptions of multiplexed pins ?continued pin name default signal alternate signal description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 33 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.26.2 multiplexing between lcd and mpmc the multiplexing between the lcd interface and mpmc a llows for the following two modes of operation: ? mpmc-mode: sdram and bus-based lcd or sram. ? lcd-mode: dedicated lcd-interface. the external nand flash is accessible in both modes. the block diagram figure 9 gives a high level overview of the modules in the chip that are involved in the pin interface multiplexing be tween the ebi, nand flash controller, mpmc, and ram-based lcd interface. figure 9 only shows the signals that are involv ed in pad-muxing, so not all interface signals are visible. fig 9. diagram of lcd and mpmc multiplexing nand_rybn[0:3] nand_ncs_[0:3] nand flash interface control control control data lcd_db_[1:0], control control control (ale, cle) ebi_a_0_ale ebi_a_1_cle ebi 2 16 data 2 6 data 16 address ebi_a_[15:2] 14 14 data lcd_db_[15:2] 14 6 ebi_ncas_blout_0 ebi_nras_blout_1 ebi_dqm_0_noe lcd_csb/ebi_nstcs_0 lcd_db_1/ebi_nstcs_1 lcd_db_0/ebi_clkout lcd_e_rd/ebi_cke lcd_rs/ebi_ndycs lcd_rw_wr/ebi_dqm_1 lcd_db_[15:2] (lcd mode)/ ebi_a_[15:2] (mpmc mode) ebi_d_[15:0] 16 data 16 address mpmc lcd address ebi_a_[1:0] 2 6 3 syscreg_mux_lcd_ebi_sel register (i/o multplexing) mpmc mode lcd mode lpc31xx 002aae157 sup4 sup8 0 1 0 1
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 34 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers the ebi unit between the nand flash interface and the mpmc contains an arbiter that determines which interface is muxed to the outside world. both nand flash and sdram/sram initiate a request to the ebi uni t. this request is granted using round-robin arbitration (see section 6.6 ). 6.26.3 supply domains as is shown in figure 9 the ebi (nand flash/mpmc-control/data) is connected to a different supply domain than the lcd interf ace. the ebi control and address signals are muxed with the lcd interface signals and are part of supply domain sup8. the sdram/sram data lines are shared with the na nd flash through the ebi and are part of supply domain sup4. therefore the following rules apply for connecting memories: 1. sdram and bus-based lcd or sram: this is the mpmc mode. the supply voltage for sdram/sram/bus-based lcd and nand flash must be the same.the dedicated lcd interface is not available in this mpmc mode. 2. dedicated lcd interface only : this is the lcd mode. th e nand flash supply voltage (sup4) can be different from the lcd supply voltage (sup8). 6.27 timer module the LPC3130/3131 contains four fully indep endent timer modules, which can be used to generate interrupts after a pre-set time interval has elapsed. this module has the following features: ? each timer is a 32 bit wide down-counter with selectable pre-scale. the pre-scaler allows using either the module clock directly or the clock divided by 16 or 256. ? two modes of operation: ? f ree-running timer: the timer generates an interrupt when the counter reaches zero. the timer wraps around to 0xffffffff and continues counting down. ? pe riodic timer: the timer generates an in terrupt when the counter reaches zero. it reloads the value from a load register an d continues counting down from that value. an interrupt will be generated every ti me the counter reaches zero. this effectively gives a repeated interrupt at a regular interval. ? at any time the current timer value can be read. ? at any time the value in the load register may be re-written, causing the timer to restart. 6.28 pulse width modul ation (pwm) module this pwm can be used to generate a pulse width modulated or a pulse density modulated signal. with an external low pass filter, the module can be used to generate a low-frequency analog signal. a typical use of the output of the module is to control the backlight of an lcd display. this module has the following features: ? supports pulse width modulation (pwm) with software controlled duty cycle. ? supports pulse density modulation (pdm) with software controlled pulse density.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 35 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 6.29 system control registers the system control registers (syscreg) module provides a register interface for some of the high-level settings in the system such as multiplexers and mode settings. this is an auxiliary module included in this over view for the sake of completeness. 6.30 i2s0/1 interfaces the i2s0/1 receive and i2s0/1 transmit modules have the following features: ? audio interface compatible with the i 2 s standard. ? i2s0/1 receive supports master mode and slave mode. ? i2s0/1 transmit supports master mode. ? supports lsb justified words of 16, 18, 20 and 24 bits. ? supports a configurable number of bit clock periods per word select period (up to 128 bit clock periods). ? supports dma transfers. ? transmit fifo (i 2 s transmit) or receive fifo (i 2 s receive) of 4 stereo samples. ? supports single 16 bit transfers to/from the left or right fifo. ? supports single 24 bit transfers to/from the left or right fifo. ? supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio sample, and the higher 16 bits representing the right audio sample. ? supports two 16-bit audio samples combined in a 32-bit word (2 left or 2 right samples) to reduce busload. ? provides maskable interrupts for audio status: fifo underrun/overrun/full/ half_full/not empty for left and right channel separately.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 36 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 7. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperatur e range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] dependent on package type. [3] human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k ser ies resistor. table 11. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min typ max unit all digital i/o pins v i input voltage ? 0.5 - +3.6 v v o output voltage ? 0.5 - +3.6 v i o output current vdde_ioc = 3.3 v - 4 - ma temperature values t j junction temperature ? 40 25 125 c t stg storage temperature [2] ? 65 - +150 c t amb ambient temperature ? 40 +25 +85 c electrostatic handling v esd electrostatic discharge voltage human body model [3] ? 500 - +500 v machine model ? 100 - +100 v charged device mo del - 500 - v
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 37 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 8. static characteristics table 12: static characteristics t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit supply pins v dd(io) input/output supply voltage nand flash controller p ads (sup4) and lcd interface (sup8); 1.8 v mode 1.65 1.8 1.95 v nand flash controller p ads (sup4) and lcd interface (sup8); 2.8 v mode 2.5 2.8 3.1 v other peripherals (sup 3) 2.7 3.3 3.6 v v dd(core) core supply voltage (sup1) 1.0 1.2 1.3 v v dd(osc_pll) oscillator and pll supply voltage on pin vdda12; for 12 mhz oscillator (sup1) 1.0 1.2 1.3 v v dd(adc) adc supply voltage on pin ad c10b_vdda33; for 10-bit adc (sup 3) 2.7 3.3 3.6 v v bus bus supply voltage on pin usb_vbus (sup5) - 5.0 - v v dda(usb)(3v3) usb analog supply voltage (3.3 v) on pin usb_vdda33 (sup 3) 3.0 3.3 3.6 v on pin u sb_vdda33_drv (sup 3); driver 2.7 3.3 3.6 v v dda(pll)(1v2) pll analog supply voltage (1.2 v) on pin u sb_vdda12_pll (sup1) 1.1 1.2 1.3 v input pins and i/o pins configured as input v i input voltage 0 - vdde_ioc v v ih high-level input voltage sup3; sup4; sup8 0.7vdde_iox (x = a, b, c) - - v v il low-level input voltage sup3; sup4; sup8 - - 0.3vdde_iox ( x = a, b, c) v v hys hysteresis voltage sup4; sup8 v 1.8 v mode 400 - 600 mv 2.8 v mode 550 - 850 mv sup3 0.1vdde_ioc - - v i il low-level input current v i = 0 v; no pull-up - - a i ih high-level input current v i = v dd(io) ; no pull-down - - a i latch i/o latch-up current ? (1.5v dd(io) ) < v i < (1.5v dd(io) ) - - ma
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 38 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers i pu pull-up current inputs with pull-up; v i = 0 sup4/sup8; 1.8 v mode a sup4/sup8; 2.8 v mode a sup3 a i pd pull-down current inputs with pull-down; v i = v dd sup4/sup8; 1.8 v mode a sup4/sup8; 2.8 v mode a sup3 a c i input capacitance excluding bonding pad cap acitance - - pf output pins and i/o pins configured as output v o output voltage - v dd(io) v v oh high-level output voltage sup4; sup8; i oh = 6 ma: 1.8 v mode v 2.8 v mode v dd(io) ? 0.26 v sup3; i oh = 6 ma v dd(io) ? 0.26 - - v sup3; i oh = 30 ma v dd(io) ? 0.38 - - v v ol low-level output voltage sup4; sup8 outputs; i ol = 4 ma 1.8 v mode v 2.8 v mode v sup3; i ol = 4 ma - - v i oh high-level output current v dd = vdde_iox (x = a, b, c); v oh = v dd ? 0.4 v - - ma v dd = vdde_iox (x = a, b, c); v oh = v dd ? 0.4 v - - ma i ol low-level output current v dd = vdde_iox (x = a, b, c); v ol = 0.4 v - - ma v dd = vdde_iox (x = a, b, c); v ol = 0.4 v - - ma i oz off-state output current v o = 0 v; v o = v dd ; no pull-up/down - - 0.064 a table 12: static characteristics t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 39 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers i ohs high-level short-circuit output current v dd = vdde_iox (x = a, b, c); v oh = 0 v - - ma v dd = vdde_iox (x = a, b, c); v oh = 0 v - - ma i ols low-level short-circuit output current v dd = vdde_iox (x = a, b, c); v ol = v dd - - ma v dd = vdde_iox (x = a, b, c); v ol = v dd - - ma z o output impedance v dd = vdde_iox (x = a, b, c) - v dd = vdde_iox (x = a, b, c) - i 2 c0-bus pins i oz off-state output current v o = 0 v; v o = v dd ; no pull-up/down - - 7.25 a v ih high-level input voltage - - v v il low-level input voltage - - v v hys hysteresis voltage - - v v ol low-level output voltage i ols = 3 ma - - 0.298 v i li input leakage current v i = - a v i = 5 v - a usb v ic common-mode input voltage high-speed mode ? 50 200 500 mv full-speed/low-speed mode 800 - 2500 mv chirp mode ? 50 - 600 mv v i(dif) differential input voltage 100 400 1100 mv table 12: static characteristics t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 40 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers [1] on pin adc10b_gnda. [2] conditions: v ssa = 0 v on pin adc10b_gnda, v dd(adc) = 3.3 v. [3] the adc is monotonic, there are no missing codes. [4] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 10 . [5] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 10 . [6] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 10 . [7] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 10 . [8] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 10 . [9] see figure 11 . table 13. adc static characteristics v dd(adc) = 2.7 v to 3.6 v; t amb = ? 40 c to +85 c unless otherwise specified; adc frequency . symbol parameter conditions min typ max unit v ia analog input voltage 0 [1] - v dd(adc) v c ia analog input capacitance - - pf n res(adc) adc resolution 2 - 10 bit e d differential linearity error [2] [3] [4] - - 1 lsb e l(adj) integral non-linearity [2] [5] - - 1 lsb e o offset error [2] [6] - - lsb e g gain error [2] [7] - - % e t absolute error [2] [8] - - lsb v err(o) offset error voltage ? 20 - +20 mv v err(fs) full-scale error voltage - mv r vsi voltage source interface resistance [9] - - k
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 41 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 10. adc characteristics 002aac046 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda ? v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 42 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers fig 11. suggested 10-bit adc interface lpc31xx adc sample ad10b_gpa[0:3] tbd k tbd pf tbd pf r vsi v ssa v ext 002aae136
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 43 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9. dynamic characteristics 9.1 lcd controller 9.1.1 intel 8080 mode [1] timing is determined by the lcd interface control register fields: invert_cs = 1; mi = 0; ps = 0; invert_e_rd = 0. see LPC3130/3131 user manual . table 14. dynamic characteristics: lcd controller in intel 8080 mode c l = 25 pf, t amb = ? 40 c to +85 c, unless otherwise specified; v dd(io) = 1.8 v and 2.8 v (sup8). symbol parameter conditions min typ max unit t su(a) address set-up time - 1 lcdcl k - ns t h(a) address hold time - 2 lcdcl k - ns t cy(a) access cycle time [1] - 5 lcdcl k - ns t w(en)w write enable pulse width [1] - 2 lcdcl k - ns t w(en)r read enable pulse width [1] - 2 lcdcl k - ns t r rise time 2 - 5 ns t f fall time 2 - 5 ns t su(d) data input set-up time - - ns t h(d) data input hold time - - ns t d(qv) data output valid delay time - ? 1 lcdc lk - ns t dis(q) data output disable time - 2 lcdcl k - ns fig 12. lcd timing (intel 8080 mode) 002aae207 mlcd_rs mlcd_csb mlcd_rw_wr, mlcd_e_rd mlcd_db[15:0] (16 bit mode), mlcd_db[15:8] (8 bit mode), mlcd_db[15:12] (4 bit mode) mlcd_db[15:0] (16 bit mode), mlcd_db[15:8] (8 bit mode), mlcd_db[15:12] (4 bit mode) t h(a) t su(a) t w(en)r and t w(en)w t d(qv) t dis(q) t su(d) t h(d) t f t r t cy(a) read access write access
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 44 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.1.2 motorola 6800 mode [1] timing is derived from the lcd interface control register fields: invert_cs = 1; mi = 1; ps = 0; invert_e_rd = 0. see LPC3130/3131 user manual . table 15. dynamic characteristics: lc d controller in motorola 6800 mode c l = 25 pf, t amb = ? 40 c to +85 c, unless otherwise specified; v dd(io) = 1.8 v and 2.8 v (sup8). symbol parameter conditions min typ max unit t su(a) address set-up time - 1 lcd clk - ns t h(a) address hold time - 2 lcd clk - ns t cy(a) access cycle time [1] - 5 lcd clk - ns t r rise time 2 - 5 ns t f fall time 2 - 5 ns t su(d) data input set-up time - - ns t h(d) data input hold time - - ns t d(qv) data output valid delay time - ? 1 l cdclk - ns t dis(q) data output disable time - 2 lcd clk - ns t w(en) enable pulse width read cycle - 2 lcd clk - ns write cycle - 2 lcd clk - ns fig 13. lcd timing (motorola 6800 mode) 002aae208 mlcd_csb mlcd_e_rd mlcd_rs, mlcd_rw_wr mlcd_db[15:0] (16 bit mode), mlcd_db[15:8] (8 bit mode), mlcd_db[15:12] (4 bit mode) mlcd_db[15:0] (16 bit mode), mlcd_db[15:8] (8 bit mode), mlcd_db[15:12] (4 bit mode) t su(d) t d(qv) t su(a) t h(a) t h(d) t f t r write access read access t dis(q) t w(en) t cy(a)
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 45 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.1.3 serial mode [1] timing is determined by the lcd interface contro l register fields: ps = 1; serial_clk_shift = 3; serial_read_pos = 3. see the LPC3130/3131 user manual . table 16. dynamic characteristi cs: lcd controller serial mode c l = 25 pf, t amb = ? 40 c to +85 c, unless otherwise specified; v dd(io) = 1.8 v and 2.8 v (sup8). symbol parameter conditions min typ max unit t cy(clk) clock cycle time [1] - 5 lcdcl k - ns t w(clk)h high clock pulse width [1] - 3 lcdcl k - ns t w(clk)l low clock pulse width [1] - 2 lcdcl k - ns t r rise time 2 - 5 ns t f fall time 2 - 5 ns t su(a) address set-up time - 3 lcdcl k - ns t h(a) address hold time - 2 lcdcl k - ns t su(d) data input set-up time - - ns t h(d) data input hold time - - ns t su(s) chip select set-up time - 3 lcdcl k - ns t h(s) chip select hold time - 1 lcdcl k - ns t d(qv) data output valid delay time - ? 1 lcdc lk - ns fig 14. lcd timing (serial mode) 002aae209 mlcd_csb mlcd_rs mlcd_db13 (serial clock) mlcd_db14 (serial data in) mlcd_db15 (serial data out) t su(d) t su(a) t h(a) t su(s) t h(s) t h(d) t d(qv) t dis(q) t f t r t w(clk)l t w(clk)h t cy(clk)
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 46 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.2 sram controller [1] refer to the LPC3130/3131 user manual for the programming of waitoen and hclk. [2] refer to the LPC3130/3131 user manual for the programming of waitrd and hclk. [3] (waitrd ? waitoen + 1) = 3 min at 60 mhz. [4] refer to the LPC3130/3131 user manual for the programming of waitwen and hclk. [5] refer to the LPC3130/3131 user manual for the programming of waitwr and hclk. [6] (waitwd ? waitwen + 1) = 3 min at 60 mhz. table 17. dynamic characteristics: static external memory interface c l = 25 pf, t amb = ? 40 c to +85 c, unless otherwise specified; v dd(io) = 1.8 v and 2.8 v (sup8). symbol parameter conditions min typ max unit common to read and write cycles t cslav cs low to address valid time - 0 - ns read cycle parameters t oelav oe low to address valid time [1] - 0 ? waitoen hclk - ns t blslav bls low to address valid time [1] - 0 ? waitoen hclk - ns t csloel cs low to oe low time - 0 + waitoen hclk - ns t cslblsl cs low to bls low time [1] - 0 + waitoen hclk - ns t oeloeh oe low to oe high time [1] [2] [3] - (waitrd ? waitoen + 1) hclk - ns t blslblsh bls low to bls high time [1] [2] [3] - (waitrd ? waitoen + 1) hclk - ns t su(dq) data input/output set-up time - 8 - ns t h(dq) data input/output hold time - 0 - ns t cshoeh cs high to oe high time - 0 - ns t cshblsh cs high to bls high time - 0 - ns t oehanv oe high to address invalid time - 2 hclk - ns t blshanv bls high to address invalid time - 2 hclk - ns write cycle parameters t csldv cs low to data valid time - 0 - ns t cslwel cs low to we low time [4] - (waitwen + 1) hclk - ns t cslblsl cs low to bls low time [4] - waitwen hclk - ns t weldv we low to data valid time [4] - 0 ? (waitwen + 1) hclk - ns t welweh we low to we high time [4] [5] [6] - (waitwr ? waitwen + 1) hclk - ns t blslblsh bls low to bls high time [4] [5] - (waitwr ? waitwen + 3) hclk - ns t wehanv we high to address invalid time - 1 hclk - ns t wehdnv we high to data invalid time - 1 hclk - ns t blshanv bls high to address invalid time - 0 - ns t blshdnv bls high to data invalid time - 0 - ns
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 47 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers fig 15. external memory read access to static memory t cshoeh t cshblsh t oehanv t blshanv t csloel t oeloeh t cslblsl t blslblsh t cslav t oelav t blslav t h(dq) t su(dq) ebi_nstcs_x ebi_dqm_0_noe ebi_ncas_blout_0 ebi_nras_blout_1 ebi_a_[15:0] ebi_d_[15:0] 002aae161
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 48 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers fig 16. external memory write access to static memory t blslblsh t cslav t csldv t wehanv t cslwel t cslblsl t wehdnv t blshdnv t blshanv t welweh t weldv 002aae162 ebi_nstcs_x ebi_ncas_blout_0 ebi_nras_blout_1 ebi_a_[15:0] ebi_d_[15:0] ebi_nwe
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 49 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.3 sdram controller [1] parameters are valid over operating tem perature range unless otherwise specified. [2] all values valid for pads set to high slew rate. vdde_ioa = vdde_iob = 1.8 0.15 v. vddi = 1.2 0. 1 v. [3] f oper = 1/t clcl table 18. dynamic characteristics of sdr sdram memory interface t amb = ? 40 c to +85 c, unless otherwise specified; v dd(io) = 1.8 v and 2.8 v (sup8). [1] [2] symbol parameter conditions min typical max unit f oper operating frequency [3] - - mhz t clcl clock cycle time - - ns t clcx clock low time - - ns t chcx clock high time - - ns t d(o) output delay time on pin ebi_cke - - 3.5 ns on pins eb i_nras_blout, ebi_ncas_blout, ebi_nwe, ebi_ndycs - - 3.5 ns on pins ebi_dqm_1, ebi_d qm_0_noe - - 5 ns t h(o) output hold time on pin ebi_cke 0.2 - 3.5 ns on pins eb i_nras_blout, ebi_ncas_blout, ebi_nwe, ebi_ndycs 0.23 - 3.5 ns on pins ebi_dqm_1, ebi_d qm_0_noe 2 - 5 ns t d(av) address valid delay time - - 5 ns t h(a) address hold time 0.1 - 5 ns t d(qv) data output valid delay time - - 9 ns t h(q) data output hold time 4 - 10 ns t su(d) data input set-up time - - ns t h(d) data input hold time - - ns t qz data output high-impedance time - - dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 50 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ebi_cke is high. fig 17. sdram burst read timing ebi_a_[15:2] ebi_dqmx ebi_d_[15:0] ebi_clkout ebi_nras_blout ebi_ncas_blout ebi_nwe ebi_cke ebi_ndycs t h(o) t h(o) t h(a) t su(d) t h(d) read nop nop nop nop nop read bank, column 002aae121 t clcl t chcx t clcx t d(o) t d(o) cas latency = 2 data n data n+1 data n+2 data n+3
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 51 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers fig 18. sdram bank activate and write timing ebi_cke write bank, row bank, column 002aae123 ebi_a_[15:2] ebi_d_[15:0] ebi_clkout ebi_nras_blout ebi_ncas_blout ebi_nwe ebi_cke ebi_ndycs t clcl t chcx t clcx t h(o) t h(o) t d(o) t d(o) t d(av) t d(qv) t h(a) t h(q) ebi_dqmx t qz active data
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 52 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.4 nand flash memory controller [1] t hclk = 1/nandflash_nand_clk, see LPC3130/3131 user manual . [2] see registers nandtiming1 and nandtiming2 in the LPC3130/3131 u ser manual . table 19. dynamic characteristics of the nand flash memory controller t amb = ? 40 c to +85 c, unless otherwise specified. symbol parameter typical unit t reh re high hold time [1] [2] t hclk x (treh+1) ns t rp re pulse width [1] [2] t hclk x (trp + 1) ns t wh we high hold time [1] [2] t hclk x (twh + 1) ns t wp we pulse width [1] [2] t hclk x (twp + 1) ns t cls cle set-up time [1] [2] t hclk x (tcls + 1) ns t clh cle hold time [1] [2] t hclk x (tclh + 1) ns t als ale set-up time [1] [2] t hclk x (tals + 1) ns t alh ale hold time [1] [2] t hclk x (talh + 1) ns t cs ce set-up time [1] [2] t hclk x (tcs + 1) ns t ch ce hold time [1] [2] t hclk x (tch + 1) ns fig 19. nand flash controller write and read timing ebi_nwe ebi_a_1_cle ebi_a_0_ale t wp t cs t ch t cls t clh mnand_ncs t wh 002aae353 t als t alh t rp t reh ebi_dqm_0_noe
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 53 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.5 crystal oscillator 9.6 spi remark: note that the signal names sck, miso , and mosi correspond to signals on pins spi_sck, spi_mosi, and spi_miso in the following spi timing diagrams. table 20: dynamic characteristics: crystal oscillator symbol parameter conditions min typ max unit f osc oscillator frequency 10 12 25 mhz clk clock duty cycle 45 50 55 % c xtal crystal capacitance input; on pin ff ast_in - - 2 pf output; on pin ff ast_out - - 0.74 pf t startup start-up time - 500 - s p drive drive power 100 - 500 w table 21. dynamic characteristics of spi pins t amb = ? 40 c to +85 c for industrial applications symbol parameter min typ max unit spi ma ster t spicyc spi cycle time ns t spiclkh spiclk high time ns t spiclkl spiclk low time ns t spidsu spi data set-up time ns t spidh spi data hold time ns t spiqv spi data output valid time ns t spioh spi output data hold time ns spi slave t spicyc spi cycle time ns t spiclkh spiclk high time ns t spiclkl spiclk low time ns t spidsu spi data set-up time ns t spidh spi data hold time ns t spiqv spi data output valid time ns t spioh spi output data hold time ns
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 54 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers fig 20. spi master timing (cpha = 1) fig 21. spi master timing (cpha = 0) sck (cpol = 0) mosi miso 002aad986 t spicyc t spiclkh t spiclkl t spidsu t spidh t spiqv data valid data valid t spioh sck (cpol = 1) data valid data valid sck (cpol = 0) mosi miso 002aad987 t spicyc t spiclkh t spiclkl t spidsu t spidh data valid data valid t spioh sck (cpol = 1) data valid data valid t spiqv
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 55 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers fig 22. spi slave timing (cpha = 1) fig 23. spi slave timing (cpha = 0) sck (cpol = 0) mosi miso 002aad988 t spicyc t spiclkh t spiclkl t spidsu t spidh t spiqv data valid data valid t spioh sck (cpol = 1) data valid data valid sck (cpol = 0) mosi miso 002aad989 t spicyc t spiclkh t spiclkl t spidsu t spidh t spiqv data valid data valid t spioh sck (cpol = 1) data valid data valid
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 56 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.6.1 texas instruments synchronous serial mode (ssi mode) [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages. remark: note that the signal names sck, miso , and mosi correspond to signals on pins spi_sck, spi_mosi, and spi_miso in the following spi timing diagram. table 22. dynamic characteristic: spi interface (ssi mode) t amb = ? 40 c to +85 c; v dd(io) (sup3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit t su(spi_miso) spi_miso set-up time t amb = 25 c; mea sured in spi master mode; see figure 24 - 11 - ns fig 24. miso line set-up time in ssi master mode t su(spi_miso) sck shifting edges mosi miso 002aad326 sampling edges
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 57 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.7 i 2 s-bus interface [1] x = 0 or 1. table 23. dynamic characteristics: i 2 s-bus interface pins t amb = ? 40 c to +85 c for industrial applications symbol parameter conditions min typ max unit common to input and output t cy(clk) clock cycle time t r rise time t f fall time output t wh pulse width high t wl pulse width low t v(q) data output valid time on pin i2stx_datax [1] on pin i2stx_wsx [1] input t su(d) data input set-up time on pin i2srx_datax [1] on pin i2srx_wsx [1] t h(d) data input hold time on pin i2srx_datax [1] on pin i2srx_wsx [1] fig 25. i 2 s-bus timing (output) 002aae361 i2stx_bck0 or i2stx_bck1 i2stx_data0 or i2stx_data1 i2stx_ws0 or i2stx_ws1 t cy(clk) t f t r t wh t wl t v(q) t v(q)
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 58 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.8 i 2 c-bus interface [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. fig 26. i 2 s-bus timing (input) 002aae362 i2srx_bck0 or i2srx_bck1 i2srx_data0 or i2srx_data1 i2srx_ws0 or i2srx_ws1 t cy(clk) t f t r t wh t su(d) t h(d) t su(d) t h(d) t wl table 24. dynamic characteristics: i 2 c-bus interface pins t amb = ? 40 c to +85 c. [1] symbol parameter conditions min typ [2] max unit f scl scl clock frequency standard mode 0 100 khz fast mode 0 400 khz t f(o) output fall time v ih to v il 20 + 0.1 c b [3] - - ns t r rise time standard mode 1000 ns fast mode 20 + 0.1 c b [3] 300 ns t f fall time standard mode 300 ns fast mode 20 + 0.1 c b [3] 300 ns t buf bus free time between a stop and start condition - t low low period of the scl clock standard mode 4.7 s fast mode 1.3 s t hd;sta hold time (repeated) start condition - t high high period of the scl clock standard mode 4.0 s fast mode 0.6 s t su;dat data set-up time standard mode 250 ns fast mode 100 ns t su;sta set-up time for a repeated start condition - t su;sto set-up time for stop condition standard mode 4.0 s fast mode 0.6 s
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 59 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.9 usb interface [1] characterized but not implemented as production test. guaranteed by design. remark: signals sd a and scl correspond to pins i2c_sdax and i2c_sclx (x = 0, 1). fig 27. i 2 c-bus pins clock timing p ss p 002aad985 t hd;sta t buf t hd;sta t su;sta t su;dat t f t high t su;sto t r t hd;sta t low sda scl table 25. dynamic characteris tics: usb pins (high-speed) c l = 50 pf; r pu = 1.5 k on d+ to v dd(io) (sup3), unless otherwise specified. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % - ns t f fall time 10 % to 90 % - ns t frfm differential rise and fall time matching t r / t f - - % v crs output signal crossover voltage - v t feopt source se0 interval of eop see figure 28 - ns t fdeop source jitter for differential transition to se0 transition see figure 28 - ns t jr1 receiver jitter to next transition - ns t jr2 receiver jitter for paired transitions 10 % to 90 % - ns t eopr1 eop width at receiver must reject as eop; see figure 28 [1] - - ns t eopr2 eop width at receiver must accept as eop; see figure 28 [1] - - ns
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 60 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 9.10 10-bit adc fig 28. differential da ta-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop table 26: dynamic characteristics: 10-bit adc symbol parameter conditions min typ max unit f s sampling frequency 10 bit resolution 400 - - ksample/s 2 bit resolution - - 1500 ksample/s t conv conversion time 10 bit resolution - - 11 clock cycles 2 bit resolution 3 - - clock cycles
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 61 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 10. application information table 27. lcd panel connections tfbga pin # pin name reset function lcd mode parallel serial lcd panel data mapping control function 16 bit 8 bit 4 bit 6800 8080 k8 mlcd_csb/ebi_nstcs0 mlcd_csb - - - lcd_csb lcd_csb lcd_csb l8 mlcd_e_rd/ebi_cke mlcd_e_rd - - - lcd_e lcd_rd - p8 mlcd_rs/ebi_ndycs mlcd_rs - - - lcd_rs lcd_rs lcd_rs n9 mlcd_rw_wr/ebi_dqm1 mlcd_rw_wr - - - lcd_rw lcd_wr - n8 mlcd_db0/ebi_clkout mlcd_db0 lcd_dbo - - - - - p9 mlcd_db1/ebi_nstcs1 mlcd_db1 lcd_db1 - - - - - n6 mlcd_db2/ebi_a2 mlcd_db2 lcd_db2 - - - - - p6 mlcd_db3/ebi_a3 mlcd_db3 lcd_db3 - - - - - n7 mlcd_db3/ebi_a4 mlcd_db4 lcd_db4 - - - - - p7 mlcd_db5/ebi_a5 mlcd_db5 lcd_db5 - - - - - k6 mlcd_db6/ebi_a6 mlcd_db6 lcd_db6 - - - - - p5 mlcd_db3/ebi_a7 mlcd_db7 lcd_db7 - - - - - n5 mlcd_db3/ebi_a8 mlcd_db8 lcd_db8 lcd_db0 - - - - l5 mlcd_db9/ebi_a9 mlcd_db9 lcd_db9 lcd_db1 - - - - k7 mlcd_db10/ebi_a10 mlcd_db10 lcd_db10 lcd_db2 - - - - n4 mlcd_db11/ebi_a11 mlcd_db11 lcd_db11 lcd_db3 - - - - k5 mlcd_db12/ebi_a12 mlcd_db12 lcd_db12 lcd_db4 lcd_db0 - - - p4 mlcd_db13/ebi_a13 mlcd_db13 lcd_db13 lcd_db5 lcd_db1 - - ser_clk p3 mlcd_db14/ebi_a14 mlcd_db14 lcd_db14 lcd_db6 lcd_db2 - - ser_dat_in n3 mlcd_db15/ebi_a15 mlcd_db15 lcd_db15 lcd_db7 lcd_db3 - - ser_dat_out
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 62 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 11. marking table 28. LPC3130/3131 marking line marking description a LPC3130/3131 basic_type
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 63 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 12. package outline fig 29. LPC3130/3131 tfbga180 package outline references outline version european projection issue date iec jedec jeita sot570-3 sot570-3 08-05-30 08-07-09 unit mm max nom min 1.20 1.06 0.95 0.40 0.35 0.30 0.50 0.45 0.40 12.1 12.0 11.9 12.1 12.0 11.9 0.8 10.4 0.15 0.08 a dimensions (mm are the original dimensions) tfbga180: thin fine-pitch ball grid array package; 180 balls 0 5 10 mm scale a 1 a 2 0.80 0.71 0.65 b d e e e 1 10.4 e 2 v w 0.05 y y 1 0.1 ball a1 index area b a d e c y c y 1 x a b c d e f h k g l j m n p 2468101214 135791113 b e 2 e 1 e e 1/2 e 1/2 e ac b v m c w m ball a1 index area detail x a a 2 a 1
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 64 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 13. abbreviations table 29. abbreviations acronym description a/d analog-to-digital adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb arm peripheral bus ata advanced transport architecture biu bus interface unit ce consumer electronics cgu clock generation unit crc cyclic redundancy check dfu device firmware upgrade dma direct memory access drm digital rights management dsp digital signal processing ebi external bus interface ecc error correction code eop end of packet esd electrostatic discharge fifo first in, first out fpga field programmable gate array gf galois field intc interrupt controller ioconfig input output configuration iom isdn oriented modular irda infrared data association irom internal rom isram internal static ram isrom internal static rom jtag joint test action group lsb least significant bit mci memory card interface mcu microcontroller unit mmc multi-media card mpmc multi-port memory controller otg on-the-go pcm pulse code modulation phy physical layer pll phase locked loop pwm pulse width modulation
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 65 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers rng random number generator rom read-only memory sd secure digital sdhc secure digital high capacity sdio secure digital input output sdr single data rate se0 single ended zero sir serial irda spi serial peripheral interface ssi serial synchronous interface syscreg system control registers tap test access port tdo test data out uart universal asynchronous receiver transmitter usb universal serial bus utmi usb 2.0 transceiver macrocell interface wdt watchdog timer table 29. abbreviations ?continued acronym description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 66 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 14. revision history table 30: revision history document id release date data sheet status change notice supersedes LPC3130_3131_1.01 preliminary data sheet - LPC3130_3131_1 modifications: ? changed pin vdde_esd (ball k11) to vdde_ioc in ta b l e 3 and ta b l e 4 . ? update cgu block diagram ( figure 6 ). LPC3130_3131_1 20090209 preliminary data sheet - -
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra LPC3130_3131_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 1.01 ? 21 may 2009 67 of 68 nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on onl y. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet wit h the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general ? information in this document is believed to be accurate and reli able. however, nxp semiconductors d oes not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make chang es to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, aut horized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these prod ucts are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in t he absolute maximum ratings system of iec 60134) may cause permanent damag e to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold su bject to the general terms and condit ions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly othe rwise agreed to in writ ing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or co nstrued as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objec tive specif ication for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra nxp semiconductors LPC3130/3131 low-cost, low-power arm926ej-s microcontrollers ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 21 may 2009 document identifier: LPC3130_3131_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . 13 6.1 arm926ej-s . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 jtag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.4 nand flash controller . . . . . . . . . . . . . . . . . . . 15 6.5 multi-port memory controller (mpmc) . . . . . . 16 6.6 external bus interface (ebi) . . . . . . . . . . . . . . 17 6.7 internal rom memory . . . . . . . . . . . . . . . . . . 17 6.8 internal ram memory. . . . . . . . . . . . . . . . . . . 18 6.9 memory card interface (mci) . . . . . . . . . . . . . 18 6.10 high-speed universal serial bus 2.0 on-the-go (otg) . . . . . . . . . . . . . . . . . . . . . 19 6.11 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 19 6.12 interrupt controller (intc). . . . . . . . . . . . . . . . 20 6.13 multi-layer ahb. . . . . . . . . . . . . . . . . . . . . . . . 21 6.14 apb bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.15 clock generation unit (cgu) . . . . . . . . . . . . . 23 6.16 watchdog timer (wdt) . . . . . . . . . . . . . . . . . 25 6.17 input/output co n figuration module (ioconfig) . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.18 10-bit analog-to-digital converter (adc10b) . 26 6.19 event router . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.20 random number generator . . . . . . . . . . . . . . 28 6.21 serial peripheral interface (spi) . . . . . . . . . . . 28 6.22 universal asynchronous receiver transmitter (uart). . . . . . . . . . . . . . . . . . . . . 28 6.23 pulse code modulation (pcm) interface . . . . 29 6.24 lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.25 i 2 c-bus master/slave interface . . . . . . . . . . . . 30 6.26 lcd/nand flash/sdram mu ltiplexing . . . . . 30 6.26.1 pin connections . . . . . . . . . . . . . . . . . . . . . . . 31 6.26.2 multiplexing between lcd and mpmc . . . . . . 33 6.26.3 supply domains . . . . . . . . . . . . . . . . . . . . . . . 34 6.27 timer module . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.28 pulse width modulation (pwm) module . . . . . 34 6.29 system control registers . . . . . . . . . . . . . . . . . 35 6.30 i2s0/1 interfaces. . . . . . . . . . . . . . . . . . . . . . . 35 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 36 8 static characteristics. . . . . . . . . . . . . . . . . . . . 37 9 dynamic characteristics. . . . . . . . . . . . . . . . . 43 9.1 lcd controller . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1.1 intel 8080 mode . . . . . . . . . . . . . . . . . . . . . . . 43 9.1.2 motorola 6800 mode . . . . . . . . . . . . . . . . . . . 44 9.1.3 serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 sram controller. . . . . . . . . . . . . . . . . . . . . . . 46 9.3 sdram controller . . . . . . . . . . . . . . . . . . . . . 49 9.4 nand flash memory controller . . . . . . . . . . . 52 9.5 crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 53 9.6 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.6.1 texas instrument s synchr onous serial mode (ssi mode). . . . . . . . . . . . . . . . . . . . . . 56 9.7 i 2 s-bus interface . . . . . . . . . . . . . . . . . . . . . . 57 9.8 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . 58 9.9 usb interface. . . . . . . . . . . . . . . . . . . . . . . . . 59 9.10 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10 application information . . . . . . . . . . . . . . . . . 61 11 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 63 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 64 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 66 15 legal information . . . . . . . . . . . . . . . . . . . . . . 67 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 67 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 67 16 contact information . . . . . . . . . . . . . . . . . . . . 67 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

▲Up To Search▲

Price & Availability of LPC3130

	To Download LPC3130 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .